Memristive Ternary Łukasiewicz Logic based on Reading-based Ratioed Resistive States (3R)

The thirst for more efficient computational paradigms has reignited interest in computation in memory (CIM), a burgeoning topic that pivots on the strengths of more versatile logic systems. Surging ahead in this innovative milieu, multi-valued logic systems have been identified as possessing the potential to amplify storage density and computation efficacy. Notably, ternary logic has attracted widespread research owing to its relatively lower computational and storage complexity, offering a promising alternative to the traditional binary logic computation. This study provides insight into the feasibility of ternary logic in the CIM domain using resistive random-access memory (ReRAM) devices. Its multi-level programming capability making it an ideal conduit for the integration of ternary logic. We focus on ternary Łukasiewicz logic because its computational characteristics are highly suitable for mapping logic values with input and output signals. This approach is characterized by voltage-reading-based output for ease of subsequent utilization and computation and validated in 1T1R crossbar arrays in an integrated ReRAM chip (Memory Advanced Demonstrator 200 mm). In addition, the effect of variability of memristive devices on logical computation and the potential for parallel operation are also investigated.