The main objective of this proposed project is to develop high performance plasmonic logic gates with small size and large on/off ratio. The developed logic gates are expected to serve as fundamental circuit elements in future high-speed optical ICs with lower thermal effect and power consumption. Unlike metal oxide semiconductor (CMOS) devices, plasmonic optical logic operations are based on wave interference without any biased voltage or current, which promises low power consumption and negligible heat generation. In this project, several basic plasmonic logic gates such as OR, XOR, XNOR, AND, NAND, and NOT are designed, fabricated, and optically characterized. The optimal basic logic gates will be assembled in a half adder and a full adder to perform complex computation.

The project is funded by DLR, IB BMBF under the number 01DO18018.